BIT-ERASING ARCHITECTURE FOR SEEK-SCAN PROBE (SSP) MEMORY STORAGE
摘要
<p>An apparatus comprising a substrate, a heater formed on the substrate, and a phase-change layer formed on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. A process comprising forming a heater on a substrate and forming a phase-change layer on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer.</p>
申请公布号
WO2008002943(A1)
申请公布日期
2008.01.03
申请号
WO2007US72163
申请日期
2007.06.26
申请人
INTEL CORPORATION;MA, QING;RAO, VALLURI, R.;CHOU, TSUNG-KUAN, ALLEN