| 摘要 |
A processor (301) for encrypting a signal to be communicated from a first location to a second location or for decrypting a signal which has been communicated from a first location to a second location, is operable to send or receive a signal which comprises a sequence (400) of frames including an initial full synchronisation frame (401) followed by consecutive mixed frames (402) each of which includes a partial frame portion (PT) of encrypted traffic information together with a partial frame portion (PS) of synchronising information. The synchronising information relates to the state of the encryption algorithm used at the transmitter, so that the algorithm at the receiver can start from the same state. The partial frame portions each contain a different part of the full synchronising information contained in the initial frame, so that the synchronising information can still be obtained at the receiver if the initial frame is missed or lost. Applications include TETRA systems. |
