CPU system, bus bridge, control method therefor, and computer system

摘要

In a system having an arrangement that a CPU ( 101 ) connected to a bus ( 107 ) via bus bridge ( 103 ) and a CPU 102 connected to a bus ( 107 ) via bus bridge ( 104 ), when the bus bridge ( 103 ) receives a semaphore acquisition request from the CPU ( 101 ), it controls acquisition of a semaphore on the basis of a semi_out signal received from the bus bridge ( 104 ) and a priority order received via a signal line ( 112 ).