发明名称 DEVICE, DESIGN AND METHOD FOR A SLOT IN A CONDUCTIVE AREA
摘要 <p>A design, device, system and process for placing slots in active regions (e.g., metal areas). Embodiments of the present invention improve the planarization of metal areas (e.g., lines) and insulators by reducing depressions (e.g., dishing) in the metal areas by including symmetric or square slots inside selected wide metal lines, by adhering to a set of placement rules. Embodiments reduce dishing in copper dual damascene structures. Embodiments reduce data processing requirements for designing and arranging the layout of IC devices and the slots.</p>
申请公布号 SG137655(A1) 申请公布日期 2007.12.28
申请号 SG20030046893 申请日期 2003.08.19
申请人 CHARTERED SEMICONDUCTOR MANUFACTURING LTD 发明人 CHOK TEE KHENG;TAN PATRICK;VIGAR DAVID;WEI CHUA TAT
分类号 G06F17/50;H01L21/768;H01L23/528;(IPC1-7):G06F17/50;H01L27/027;H01L23/52 主分类号 G06F17/50
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