发明名称 |
Delay calculating method in semiconductor integrated circuit |
摘要 |
An input pin capacitance of a cell is obtained in advance in a function expression, and a delay is calculated in such manner that the input pin capacitance is calculated in functions of an input slew and a drive load capacitance in each instance. In a cell characterizing process, a total volume of a current running into an input terminal before a voltage value of the input terminal reaches a reference voltage is obtained so that a value approximate to a real input pin capacitance can be obtained.
|
申请公布号 |
US2007300196(A1) |
申请公布日期 |
2007.12.27 |
申请号 |
US20050296640 |
申请日期 |
2005.12.08 |
申请人 |
ISHIBASHI NORIKO;HIRATA MASAAKI;IWANISHI NOBUFUSA |
发明人 |
ISHIBASHI NORIKO;HIRATA MASAAKI;IWANISHI NOBUFUSA |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|