发明名称 SIGNAL SELECTING CIRCUIT AND VARIABLE DELAY CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a technique capable of suppressing occurrence of a phenomenon in which a time from input to output varies depending on signals to be selected. <P>SOLUTION: A plurality of selectors each capable of selecting and inputting any one of M-items of input signals to an output terminals are juxtaposed, and a hierarchy from a first selector stage for selecting M<SP>N-1</SP>-items of output from M<SP>N</SP>-items of input terminals to an N-th selector stage consisting of one selector is built by successively reducing the multiplier N one by one. The signal selecting circuit is provided with a selector layer 101; and a wiring layer 102 where wiring is executed on each of stages from the first selector stage to the N-th selector stages, and the wiring is performed between input/output terminals of each of the selectors so that the wiring for an (mm≤M)th input terminal of each selector can cross the wiring an M'th input terminal. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2007336024(A) 申请公布日期 2007.12.27
申请号 JP20060163014 申请日期 2006.06.13
申请人 TOSHIBA CORP;TOSHIBA SOLUTIONS CORP 发明人 TANIGUCHI MITSUHIDE
分类号 H03K5/13;H03K5/00 主分类号 H03K5/13
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