| 摘要 |
<p>A method for manufacturing a flash memory device is provided to suppress generation of a void between a first element and a second element by removing a TEOS layer as a top layer of a spacer. An isolation layer(33) is formed on a semiconductor substrate(31) in order to define unit cell elements(61,63) including a first and second cell regions. A gate oxide layer(35), a floating gate(37), an ONO layer(39), and a control gate(41) are formed on each of the first and second cell regions. A spacer including a first TEOS layer(43), a silicon nitride layer(45), and a second TEOS layer is formed on both sides of the gate oxide layer, the floating gate, the ONO layer, and the control gate. A source/drain region(49) is formed on the semiconductor substrate of both sides of the control gate. A silicide layer(51) is formed on the control gate and the source/drain region. The second TEOS layer is removed from the spacer by performing an etch process. A via hole is formed to expose the silicide layer on the drain region by forming and patterning an interlayer dielectric on the semiconductor substrate. A contact plug is formed within the via hole.</p> |
