| 摘要 |
A computational unit, or node, in an adaptive computing engine uses a uniform interface to a network to communication with other nodes and resources. The uniform interface is referred to as a "node wrapper." The node wrapper includes a hardware task manager (HTM), a data distributor, optional direct memory access (DMA) enging and a data aggregator. The hardware task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The HTM coordinates a nodes assignment tasks using a task lists. A "ready-to-run queue" is implemented as a first-in first-out stack. The HTM uses top-level finite-state machine (FSM) that communicates with a number of subordinate FSMs to control individual HTM components. The Data Distributor interfaces between the node's input pipeline register and various memories and registers with the node. Different types of data distribution are possible based upon the values in service and auxiliary fields of a 50-bit control structure. The Data Aggregator arbitrates among up to for node elements that request access to the node's output pipeline register for the purpose of transferring data to the intended sestination via the network. The DMA Engine uses a five-register model. The registers include a Startin Address Register, an Address Stride Register, a Transfer Count Register, a Duty Cycle Register, and a Control Register including a GO bit, Target Node number / port number, and DONE protocol. A control node, or "K-node," is used to control various aspects of the HTM, data distributor, data aggregator and DMA operations within the nodes of the system. |
