发明名称 |
METHOD AND DELAY CIRCUIT WITH ACCURATELY CONTROLLED DUTY CYCLE |
摘要 |
<p>A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock (8) signal and the data synchronization signal and produces a delay control signal. A first delay circuit (11) produces a signal which is delayed relative to the data clock signal according to the delay control signal. A second delay circuit receiving the delayed signal produces a control signal coupled to a control input of the storage element by delaying the delayed signal an amount which causes the control signal to have a predetermined duty cycle.</p> |
申请公布号 |
WO2007150056(A2) |
申请公布日期 |
2007.12.27 |
申请号 |
WO2007US71959 |
申请日期 |
2007.06.25 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED;WHITE, ROBERT, L. |
发明人 |
WHITE, ROBERT, L. |
分类号 |
H03K3/017 |
主分类号 |
H03K3/017 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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