| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory interface device for reducing a CPU processing time relating to binary data in an image processor compared with a conventional technology. SOLUTION: A memory interface device installed between a memory 20 and a CPU 10 is provided with a means 34 for dividing an address output from the CPU 10 into a lower rank address and an upper rank address, and for reading binary image data whose bits are respectively are associated with one pixel by word or byte units from the memory 20 based on the upper rank address; a means 36 for selecting one bit from the read image data as binary data for one pixel based on the lower rank address; and a means 38 for storing the selected binary data for one pixel by assigning the data to predetermined one or more bits in the word or byte, and for transmitting the read data including the binary data for one pixel per word or byte to the CPU 10. COPYRIGHT: (C)2008,JPO&INPIT
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