发明名称 Line memory packaging apparatus and television receiver
摘要 According to one embodiment, using several random access memory components, these several RAM components are integrally driven to form a logical line memory. The number of using RAM components is reduced to the minimum, and thereby, hardware cost is reduced. A line memory forming apparatus comprises cascade-connected several RAM components, several line memories logically serial-connected in a manner that of the several RAM components, part of an output of the final-stage RAM component and part of an input of the first-stage RAM component are provided with several connection portions, and a controller controlling write address and read address of the several RAM components to drive the line memories.
申请公布号 US2007296872(A1) 申请公布日期 2007.12.27
申请号 US20070812453 申请日期 2007.06.19
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 YAMASAKI MASAYA;OGAWA YOSHIHIKO
分类号 H04N9/64;G06T1/60;H04N5/44 主分类号 H04N9/64
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