| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of achieving compatibility of a circuit scale reduction and the improvement of signal delay time. <P>SOLUTION: A wordline drive circuit 21 for driving each of wordlines (22a, 22b, 22c, 22d,...) is arranged in one direction only of single side of a memory cell array 10. In the wordlines of odd numbered rows among small areas which are constituted by dividing the upper area of each wordline into nearly two equal parts in the row direction, pieces of low resistance wiring (25a, 25c,...) are formed on small areas at the side (left side in figure 3) where the wordline drive circuit 21 is present, meanwhile in the wordline of even numbered rows, pieces of low resistance wiring (25b, 25d,...) are formed on small areas at the opposite side (right side in figure 3) of the word drive circuit 21. By this arrangement, the reduction in resistance values of wordlines from the word drive circuit to a memory cell and also suppression of variance in resistance values of wordlines from the word drive circuit to each memory cell at the same column position are attained while evading short circuits of the pieces of low resistance wiring related to the adjacent rows. <P>COPYRIGHT: (C)2008,JPO&INPIT |
