| 摘要 |
A semiconductor memory device includes a memory cell, a word line, a bit line, a column gate, and a power supply decode circuit. The memory cell has a first MOS transistor including a charge accumulation layer and a control gate. The bit line is connected to a drain of the first MOS transistor and is applied with first voltage at the test operation time and at data program operation time. The column gate includes a second MOS transistor having current path connected to the bit line to transfer the first voltage to the bit line at the test operation time. The power supply decode circuit applies a second voltage to a gate of the second MOS transistor at the program operation time and applies a third voltage lower than the second voltage at the test operation time.
|
