发明名称 |
Wafer level chip scale package having a gap and method for manufacturing the same |
摘要 |
A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.
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申请公布号 |
US7312143(B2) |
申请公布日期 |
2007.12.25 |
申请号 |
US20070717691 |
申请日期 |
2007.03.14 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
PARK MYEONG-SOON;CHUNG HYUN-SOO;LEE IN-YOUNG;CHUNG JAE-SIK;SIM SUNG-MIN;JANG DONG-HYEON;SONG YOUNG-HEE;RYU SEUNG-KWAN |
分类号 |
H01L23/48 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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