| 摘要 |
A process for producing a layer arrangement, which layer arrangement allows a dual gate field-effect transistor to be formed. In this process, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate. A first semiconductor layer is formed on the sacrificial layer, and a first electrically insulating layer is formed on the first semiconductor layer. An electrically conductive layer is formed on the first electrically insulating layer, which electrically conductive layer is laterally patterned. The first electrically insulating layer, the sacrificial layer and the first semiconductor layer are jointly laterally patterned using the laterally patterned electrically conductive layer as a mask. Furthermore, a semiconductor structure is formed adjacent to side walls of the patterned sacrificial layer and of the patterned first semiconductor layer. A substrate is secured over the patterned electrically conductive layer, and material of the auxiliary substrate is removed, so that the sacrificial layer is uncovered. Furthermore, the sacrificial layer is selectively removed, so as to form a trench, and a second electrically insulating layer is formed in the trench, then an electrically conductive structure is formed on this second electrically insulating layer.
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