发明名称 Reset detection circuit in semiconductor integrated circuit
摘要 A reset detection circuit for a logic circuit and a RAM includes a first determining circuit, a second determining circuit and a reset signal generating circuit. The first determining circuit operates with a first voltage and determines whether a second voltage is equal to or higher than a reset voltage for the logic circuit. The second determining circuit operates with the first voltage and determines whether the first voltage is equal to or higher than a minimum operating voltage as a guarantee voltage for an operation of the first determining circuit. The reset signal generating circuit outputs a reset signal for resetting the logic circuit and the RAM, when the first voltage is lower than the minimum operating voltage and the second voltage is lower than the reset voltage.
申请公布号 US7313048(B2) 申请公布日期 2007.12.25
申请号 US20070714203 申请日期 2007.03.06
申请人 DENSO CORPORATION 发明人 ISHIKAWA YASUYUKI;SUZUKI AKIRA;ISHIHARA HIDEAKI
分类号 G11C29/52;G05F1/10;G05F3/02 主分类号 G11C29/52
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