发明名称 Internally generating patterns for testing in an integrated circuit device
摘要 In a first integrated circuit chip contained in a single package along with a second integrated circuit chip, a system includes circuitry on the first integrated circuit chip for receiving address signals from the second integrated circuit chip during normal operation. Circuitry on the first integrated circuit chip generates address signals for use in testing the first integrated chip in a test mode.
申请公布号 US7313740(B2) 申请公布日期 2007.12.25
申请号 US20050083473 申请日期 2005.03.18
申请人 INAPAC TECHNOLOGY, INC. 发明人 ONG ADRIAN E.
分类号 G11C29/00;G01R31/3181;G11C29/20 主分类号 G11C29/00
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