发明名称 SEMICONDUCTOR MEMORY WITH RESET FUNCTION
摘要 A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC includes an input buffer configured to generate a buffered reset signal RST from the external Reset signal. The SDRAM IC further includes a reset circuit is configured to generate an internal reset signal Reset En from (a) the RST signal, (b) a clock enable signal CKE which indicates a time when the SDRAM is ready to receive an external command, and (c) a mode register programming signal MRSP which indicates a time when a mode register is to be loaded with data.
申请公布号 WO2007033357(A3) 申请公布日期 2007.12.21
申请号 WO2006US35973 申请日期 2006.09.13
申请人 HYNIX SEMICONDUCTOR INC.;LEE, IHL-HO 发明人 LEE, IHL-HO
分类号 G11C7/20;G11C7/22 主分类号 G11C7/20
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