| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a phase locked loop capable of providing a plurality of output clock signals synchronized with an input clock signal with an adjustable relative phase difference. <P>SOLUTION: A controllable oscillator DCO generates an output signal CKout of the phase locked loop, and a phase detector PD determines a phase difference between an input clock signal CKin of the PLL 12 and the PLL output signal CKout, and provides a phase detector output signal synchronizing the oscillator DCO with the clock signal CKin being used. Here, in order to be able to provide a plurality of PLL output signals with an adjustable relative phase difference that are synchronized with the clock signal CKin, provision is made that for the determination of the phase difference, an adjusted phase-shifted version CK<1:8> of the output signal CKout of the PLL is generated and compared with the phase of the clock signal being used as CKin, and that the adjusted phase-shifted version CK<1:8> of the PLL output signal CKout is provided as a further PLL output signal CK<1:8>. <P>COPYRIGHT: (C)2008,JPO&INPIT |
