| 摘要 |
PROBLEM TO BE SOLVED: To solve such a problem that it is difficult to monitor multiple pieces of internal information since many terminals are required to output trace information to the outside when verification of bus performance is performed, however, the number of terminals are limited. SOLUTION: Input data effective timing information Ain indicating effective timing of input data Din, and a block 2 to be debugged for generating and outputting output data effective timing information Aout indicating effective timing of output data Dout are monitored. The bus monitoring circuit comprises: a control circuit 4 for inputting the input data effective timing information Ain and the output data effective timing information Aout to generate and output a holding timing signal Shd and a comparison timing signal Scm; a data holding circuit 5 for holding the input data Din in synchronization with the holding timing signal Shd; and an inequality detection circuit 6 for determining inequality between the holding data Hin from the data holding circuit 5 and the output data Dout from the block 2 to be debugged in synchronization with the comparison timing signal Scm to generate and output an inequality detection signal Sr. COPYRIGHT: (C)2008,JPO&INPIT
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