发明名称 FIELD PROGRAMMABLE PROCESSOR ARRAYS
摘要 PROBLEM TO BE SOLVED: To provide a dense circuit layout, efficient interconnections between processing units and flexibility in the manner in which the processing units may be interconnected. SOLUTION: The present invention relates to an integrated circuit. In this integrated circuit, some of circuit areas 12 each provide a respective processing unit for performing operations on data on at least one respective input signal path (an, aw, be, bs, hci, vci) to provide data on at least one respective output signal path (fn, fe, fs, fw, vco, hco). Other of the circuit areas each provide a respective switching section 14, and the processing units and the switching sections are arranged alternately in each row and in each column. Each of a substantial proportion of the switching sections provides a programmable connection 16, 18, 20 between at least some of the signal paths of those of the processing units adjacent that switching section in the same column and in the same row. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007329936(A) 申请公布日期 2007.12.20
申请号 JP20070165208 申请日期 2007.06.22
申请人 ELIXENT LTD 发明人 MARSHALL ALAN;STANSFIELD TONY;VUILLEMIN JEAN
分类号 H03K19/177;G06F15/78;H01L21/82 主分类号 H03K19/177
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