发明名称 PLL SYNTHESIZER AND LOCK DETECTOR
摘要 <P>PROBLEM TO BE SOLVED: To provide a PLL synthesizer that can have statisfactory properties of fast actuation, low power consumption, and low spuriousness in a stationary state at the same time, and a lock detector which detects acquisition of synchronism. <P>SOLUTION: The PLL synthesizer which pulls in the frequency and phase of the output signal of a voltage-controlled oscillator with phase locked loop (PLL) constitution using a switching type variable frequency divider is equipped with the lock detector which monitors the control voltage Vvco of the voltage-controlled oscillator, decides whether its variation quantity &Delta;Vvco is larger or smaller than a predetermined range, and outputs a synchronism decision signal when the variation quantity &Delta;Vvco of the control voltage becomes smaller than the predetermined range. <P>COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007329716(A) 申请公布日期 2007.12.20
申请号 JP20060159525 申请日期 2006.06.08
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 NAKAMURA MITSUO;YAMAGISHI AKIHIRO;TSUKAHARA TSUNEO;HARADA MITSURU
分类号 H03L7/183;H03L7/197 主分类号 H03L7/183
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