发明名称 METHOD OF FORMING A METAL LINE IN A SEMICONDUCTOR DEVICE
摘要 A method for forming a metal line of a semiconductor device is provided to reduce a resistance of a wiring by forming an insulating layer after forming the wiring and a via plug. A semiconductor substrate(101) having a predetermined structure is provided. A wetting layer, a first metal layer(104), an etch stop film(105), and a second metal layer(106) are sequentially formed on the semiconductor substrate. A metal stud is formed by patterning the second metal layer. A wiring is formed by patterning sequentially the etch stop film, the first metal layer, and the wetting layer. An interlayer dielectric is formed on an upper part of an entire structure. A lower metal wiring including the wiring and the metal stud is formed by exposing the metal stud. An upper metal wiring is formed by performing repeatedly all processes.
申请公布号 KR20070119173(A) 申请公布日期 2007.12.20
申请号 KR20060053429 申请日期 2006.06.14
申请人 JUSUNG ENGINEERING CO., LTD. 发明人 LEE, SANG HYEOB
分类号 H01L21/3205;H01L21/28 主分类号 H01L21/3205
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