| 摘要 |
A system for determining the target address of a branch instruction is disclosed. The system includes: a branch target buffer (BTB), containing at least an entry storing the target address of the branch instruction, the entry being indexed according to a program counter (PC) value of an instruction prior to the branch instruction; a PC register, containing a PC value of a current instruction; and a comparator, coupled to the PC register and the BTB, for comparing the PC value of the current instruction with an output of the BTB corresponding to a previous instruction.
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