| 摘要 |
The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding semiconductor structure. The method comprises the steps of: providing a semiconductor substrate having a plurality of trench capacitors which are arranged in rows and columns in a checkerboard layout; forming connection straps for electrically connecting said trench capacitors such that the connection straps of pairs of adjacent columns are facing each other, forming insulation trenches between said rows for defining active areas, each of which active areas is electrically connected to a connection strap of an associated trench capacitor on a first side and each of which is electrically insulated from a neighboring trench capacitor of said associated trench capacitor on a second side; forming electrically conducting landing pads between adjacent active areas for connecting pairs of said active areas, said landing pads being arranged in first lines in parallel to said columns; forming an insulation layer on said first insulating layer covering said landing pads; and forming a cell transistor for each trench capacitor which divides the active area of the associated trench capacitor in a first and second section, said cell transistors being arranged in second lines in parallel to said columns.
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