| 摘要 |
<p>At least two EOR circuits for carry-out which output carry-out bits and the complementary signals thereof are provided in the 5-3 compressor circuits constituted by an EOR circuit group, and dual lanes are employed at least for carry-out. As a result, the number of inverters required can be reduced, increases in delay time can be suppressed, and fast addition operation can be achieved.</p> |
