Method for forming mulitlevel interconnects in semiconductor device

摘要

A method for forming a multilevel interconnects in a semiconductor device. In the multilevel interconnects forming method, a conductive layer pattern (130) is formed on a semiconductor substrate including a first insulating layer (120), to a thickness of Y1. A second insulating layer (140) is formed on the overall surface of the resultant including the conductive layer pattern (130). A lower conductive layer pattern is formed to a thickness of 2×Y1/3 on the second insulating layer to be separated from the conductive layer pattern by at least 3xY1. On the overall surface of the resultant including the lower conductive layer pattern (150a,150b) is formed a third insulating layer (160). A planarization layer (170) is formed of spin-on-glass (SOG) on the third insulating layer (160) to expose the third insulating layer on the conductive layer pattern (130) and the lower conductive layer pattern (150a,150b). By forming this planarization layer, conductive layer pattern-induced fine cracks can be prevented from being produced on the SOG of a step portion.