发明名称 Self-biased phased-locked loop
摘要 In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input, a second control input, and a third control input, wherein the first control input, the second control input, and the third control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the first charge pump, the second charge pump, and the first bias generator. A third bias generator is coupled to the third control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.
申请公布号 US7310020(B2) 申请公布日期 2007.12.18
申请号 US20050321495 申请日期 2005.12.29
申请人 INTEL CORPORATION 发明人 TAN SWEE BOON;WONG KENG L.
分类号 H03L7/00;H03L7/099 主分类号 H03L7/00
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