| 摘要 |
A shift register and a driving method thereof are provided to prevent output signals from respective stages from being overlapped with each other by outputting first and second clock signals at different timings. A shift register includes plural stages, which receive first and second clock signals, delay a phase of a start signal, and output an output signal. The respective stages include first to third transistors. A gate terminal of the first transistor is connected to a gate terminal of the second transistor. The gate terminals of the first and second transistors are commonly connected to an input line of the second clock signal(CLK2). A first terminal of the first transistor is connected to an input line. A first terminal of the second transistor is connected to a second voltage terminal. A second terminal of the second transistor is connected to a first terminal of the third transistor. The second terminal of the second transistor and a first terminal of the third transistor are commonly connected to an output line. A second terminal of the third transistor is connected to the input line for the first clock signal(CLK1). The second terminal of the first transistor and a gate terminal of the third transistor are connected to a node, which is connected to a first voltage terminal. A capacitor is connected between the node and the first voltage terminal.
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