| 摘要 |
A fuse line of a semiconductor device is provided to prevent a malfunction of the fuse line in a blowing process by forming a first and a second fuse lines separated to each other. A conductive pattern(33) is formed on a first interlayer dielectric(32) in a fuse region of a semiconductor substrate(31), to be connected with a power voltage supplier(VDD). A second interlayer dielectric(34) is formed to fill the conductive pattern. A first and a second fuse lines(37a,37b) are formed to be separated to each other, and overlapped respectively with adjacent side parts of the conductive pattern. A third interlayer dielectric(38) is formed on the fuse lines. A first plug(39a) is formed within the second and the third interlayer dielectrics, and contacted simultaneously to the ends of the first fuse line and the conductive pattern. A second plug(39b) is formed to be contacted simultaneously to the ends of the second fuse line and the conductive pattern. A first and a second wiring(40a,40b) are formed on the first and the second plugs.
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