发明名称 EXPONENTIATION ARITHMETIC UNIT, DECODING APPARATUS, AND SIGNATURE CREATING APPARATUS
摘要 PROBLEM TO BE SOLVED: To solve the following problem: the conventional method for blocking the attack of simple power analysis by adding dummy multiplication to eliminate the differences in existence of multiplication by the bit of a power value of a private key (d) cannot block an attack (a BigMac attack) wherein the multipliers in a dummy multiplication and in a non-dummy multiplication are analyzed. SOLUTION: An exponentiation arithmetic unit comprises an input/output section, a private key storing section, a counter storing section, a counter initializing section, a counter updating section, a first counter judging section, a second counter judging section, a bit judging section, a multiplication section, a squaring section, an intermediate value storing section, a multiplier storing section, a random number storing section, a multiplier initializing section, a multiplier updating section, a randomness removing section, and a random number updating section. By updating the multiplier while raising it, distinction between a dummy multiplication and a non-dummy multiplication is made difficult. Thus, a BigMac attack can be blocked. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007316491(A) 申请公布日期 2007.12.06
申请号 JP20060148059 申请日期 2006.05.29
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 FUDA YUICHI;MATSUZAKI NATSUME
分类号 G09C1/00;H04L9/10 主分类号 G09C1/00
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