| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock switching circuit for preventing a short pulse from being generated in an output clock even when a clock having different phases is switched based on an asynchronous switching signal. <P>SOLUTION: A clock switching circuit 1 is provided with PLL circuits 2 and 3 to which external clock CLKT and CLKB are respectively input; a multiplexer 14 for selectively outputting the inversion signal of the output PLB of the PLL circuit 3 or the output PLT of the PLL circuit 2; and a clock control circuit 13 for controlling the switching of the multiplexer 14 based on a Lock decision signal 12a which is asynchronous with the CLKB and PLB. When the Lock decision signal 12a is input, the clock control circuit 13 controls the multiplexer 14 to switch the output synchronously with an offset clock PLQB acquired by offsetting the phase of the PLB by a predetermined value. <P>COPYRIGHT: (C)2008,JPO&INPIT |
