| 摘要 |
PROBLEM TO BE SOLVED: To appropriately deal with parasitic components in coincidence verification of a circuit diagram and a layout. SOLUTION: This method for designing a semiconductor device includes a step for creating the circuit diagram containing electric elements, a step for creating layout data containing a real layout pattern indicating the structure of the electric element, a step for determining a predetermined electrical property value of the electric element achieved by the layout pattern from at least one of simulation or measurement, a step for adding a pseudo-layout pattern indicating the determined electrical property value to the layout data, and a step for verifying whether or not the layout data exhibits the circuit diagram with an LVS (Layout versus Schematic) tool. The LVS tool calculates the electrical property value using the pseudo-layout pattern. COPYRIGHT: (C)2008,JPO&INPIT
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