Power-level circuit-arrangement, has four transistors switched between operating voltage and base voltage, where drain-connections of two transistors are switched to output terminal

摘要

The arrangement has four transistors (T1p,T2n,T3p,T4n) switched between operating voltage (VDD) and base voltage (VSS). The drain-connections of two transistors are switched to other output terminal (O1), and the drain-connections of other two transistors are switched to output terminal (O2). The gate-connections of the former and the fourth transistor or the gate connections of the latter and the third transistor are connected with one another for common switching of the former and the fourth transistor or for common switching of the latter and the third transistor by a switching device. An independent claim is also included for the method for operation of power-level circuit-arrangement.