发明名称 METHOD FOR EVALUATING SOI WAFER
摘要 <p>Provided is a method for evaluating sheet resistance of an embedded diffusion layer of an SOI wafer. The SOI wafer has at least an SOI layer on an insulating layer, and the embedded diffusion layer having an impurity concentration higher than that of other regions of the SOI layer, on the SOI layer at an interface region of the SOI layer and the insulating layer. The method for evaluating the SOI wafer is provided with a step of measuring the sheet resistance of the entire SOI layer or that of the entire SOI wafer, and a step of estimating the sheet resistance of the embedded diffusion layer by conversion by regarding the results of the sheet resistance measurement as resistance wherein layers constituting the SOI wafer are connected in parallel. Thus, direct measurement of the SOI wafer itself to be a product is made possible without manufacturing a monitor wafer, and the sheet resistance of the embedded diffusion layer can be evaluated.</p>
申请公布号 WO2007138828(A1) 申请公布日期 2007.12.06
申请号 WO2007JP59639 申请日期 2007.05.10
申请人 SHIN-ETSU HANDOTAI CO., LTD.;YOSHIDA, KAZUHIKO 发明人 YOSHIDA, KAZUHIKO
分类号 H01L27/12;H01L21/66 主分类号 H01L27/12
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