发明名称 OPERATIONAL AMPLIFIER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an operational amplifier circuit capable of suitably suppressing the generation of offset voltage. SOLUTION: The operational amplifier circuit has a transistor P11 whose source is connected to a drain of a transistor P3 of an output stage circuit 30 and whose drain is connected to a drain of a transistor N5. A source of a transistor N12 is connected to a gate of the transistor P11. A first input signal IP is impressed on a gate of the transistor N12. Namely, potential V3 of a node C between the transistors P3 and P11 becomes voltage which falls off by voltage Vgs1 between sources and rises for voltage Vgs2 between gate and source of the transistor P11. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007318571(A) 申请公布日期 2007.12.06
申请号 JP20060147469 申请日期 2006.05.26
申请人 FUJITSU LTD 发明人 HATANAKA TAKUYA
分类号 H03F3/34;H03F3/45 主分类号 H03F3/34
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