| 摘要 |
A refresh circuit for refreshing a memory device is proposed. The refresh circuit includes: reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells each one having a reference threshold voltage, means for detecting the reaching of a comparison current by a cell current of each memory cell and by a reference current of each reference cell, and means for determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and the reference currents, and writing means for applying a writing voltage to at least one selected of the memory cells; the refresh circuit further includes control means for enabling the writing means during at least part of the application of the biasing voltage after the determination of the condition of each selected memory cell.
|
