SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To lower a defective fraction and to prevent an increase in area even though a redundant layout design for intending to improve an LSI yield is provided. SOLUTION: The redundant via hole 54 exists in the layout of an interconnection of the LSI. The limit for the design rule of an interconnection 52 connected to the redundant via hole 54 is farther relaxed in the layout design than the limit for the design rule of the interconnection 52 connected to the ordinary via hole 53 when no redundant via hole 54 exists. COPYRIGHT: (C)2008,JPO&INPIT