发明名称 Dll Circuit
摘要 A DLL circuit comprises a dummy delay corresponding to an internal clock delay from an external clock, a variable delay addition circuit having a coarse and fine delay circuits adjusting delay amount according to a delay amount adjustment signal, and a phase comparison circuit comparing phases of the internal clock and a delay clock input via the variable delay addition circuit and the dummy delay and outputting the delay amount adjustment signal to the variable delay addition circuit. At the start of burst, a first signal set at a logic "1" during 1 clock cycle of the internal clock is input to the variable delay addition circuit via the dummy delay, and duration time of the logic "1" of the first signal is detected until 1 clock cycle of the internal clock is completed and delay amount of the variable delay addition circuit is initialized by setting one of the coarse delay circuit based on the duration time.
申请公布号 US2007279113(A1) 申请公布日期 2007.12.06
申请号 US20050590225 申请日期 2005.02.09
申请人 MAEDA KENGO;TANIGAWA AKIRA;NISHIYAMA MASUJI;OHORI SHOICHI;HIRANO MAKOTO;TAKASHIMA HIROSHI;MATOBA SHINJI;ASANO MASAMICHI 发明人 MAEDA KENGO;TANIGAWA AKIRA;NISHIYAMA MASUJI;OHORI SHOICHI;HIRANO MAKOTO;TAKASHIMA HIROSHI;MATOBA SHINJI;ASANO MASAMICHI
分类号 G11C16/02;H03L7/06;G01F1/12;G06F1/10;G11C11/4063;G11C16/32;H03H11/26;H03K5/13;H03K5/1534;H03L7/08;H03L7/081 主分类号 G11C16/02
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