发明名称 |
Signal Output Circuit, Audio Signal Output Apparatus Using The Same, And Electronic Device |
摘要 |
A selection circuit switches the output between a ancillary PWM signal NS<SUB>PWM </SUB>and a primary PWM signal S<SUB>PWM </SUB>in accordance with a power supply transition period or normal period. A ancillary signal generating circuit generates a gradually rising signal which is then amplified by a second driver circuit, so that a DC block capacitor is gradually charged and discharged. Thereby, the occurrence of noise due to an inrush current is prevented.
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申请公布号 |
US2007279101(A1) |
申请公布日期 |
2007.12.06 |
申请号 |
US20050578813 |
申请日期 |
2005.04.20 |
申请人 |
ONODERA TAKESHI;MUNENAGA HIDEKI;SAKAIDANI SATOSHI |
发明人 |
ONODERA TAKESHI;MUNENAGA HIDEKI;SAKAIDANI SATOSHI |
分类号 |
H03K5/00;H03F1/00;H03F1/26;H03F3/217 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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