| 摘要 |
A memory device is disclosed. A floating gate is disposed overlying a substrate. A tunneling dielectric layer is interposed between the floating gate and the substrate. An inter poly dielectric layer is disposed overlying the floating gate and the substrate. A word line is disposed overlying the floating gate, extending in a row direction. A bit line is disposed in the substrate, extending in a column direction, wherein the bit line is partially overlapped by the floating gate and the word line.
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