| 摘要 |
A cache memory device (30) includes a command receiving unit that receives a plurality of commands from each of a plurality of processors; a processing unit (304) that performs a process based on each of the commands; and a storage unit (301) that stores in a queue (330) a first command, when the command receiving unit (301) receives the first command while the processing unit (304) is processing a second command, a cache line address corresponding to the first command being identical to the cache line address corresponding to the second command which is being processed by the processing unit (304).
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