| 摘要 |
A multi-mode quadrature digital down-converter and a front-end module are provided to solve a problem that when an IF(Intermediate Frequency) signal lower than 1MHz is sampled with 4.096MHz, a pattern of the sampled value varies so the IF signal cannot be normally processed. A demultiplexer(210) converts a digital IF signal into a pre-set number of parallel signals. A selector(220) is turned on or off according to a broadcast select signal. When the selector is turned on, it selects some of the parallel signals of the demultiplexer(210), and when the selector is turned off, it selects all the parallel signals of the demultiplexer(210). A buffer memory(230) includes a buffer space with a pre-set size for sequentially storing signals from the selector(220) and, in this case, the buffer space includes multiple buffer regions discriminated by sizes in the order of storing the signals from the selector(220). A digital filter unit(240) multiplies each signal stored in the same position in terms of the storage order in each buffer region of the buffer memory(230) to a pre-set filter coefficient, adds the values obtained by the multiplication, and outputs the same. An adding unit(250) adds pre-set signals among the values of the addition in the digital filter unit(240). An inverter(260) inverts an I signal and a Q signal from the adding unit(250) and outputs a quadrature signal.
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