| 摘要 |
<p>A method for forming an alignment key of a semiconductor device is provided to minimize damage of the alignment key due to a planarization process by securing a step in an alignment key region from a process for forming an isolation layer. A semiconductor device(111) is partially etched by an etching process using an exposure mask for defining an alignment key region to form a trench. An oxide layer(115) is formed to gap-fill a part of the trench. A conductive layer(117) for a gate is formed on an upper portion of the entire surface. The conductive layer for a gate is etched by an etching process using the exposure mask to expose the oxide layer. A first interlayer dielectric(121) is formed on the upper portion of the entire surface. The first interlayer dielectric is etched by an etching process using the exposure mask to expose the oxide layer. A second interlayer dielectric(125) is formed on an upper portion of the entire surface. The second interlayer dielectric is etched by an etching process using the exposure mask for defining a box-in-box shaped alignment key to form an alignment key for exposing the oxide layer.</p> |
