发明名称 Methodology for image fidelity verification
摘要 A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-dimensional printed image of the critical width integrated circuit segment is simulated. The method then includes determining a ratio of perimeters or areas of the designed critical width integrated circuit segment to the simulated printed critical width integrated circuit segment, and predicting functionality of the critical width integrated circuit segment after printing based on the ratio of perimeters or areas.
申请公布号 US7305334(B2) 申请公布日期 2007.12.04
申请号 US20050908724 申请日期 2005.05.24
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 GRAUR IOANA;LAI KAFAI;SINGH RAMA N.
分类号 G06F17/50 主分类号 G06F17/50
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