发明名称 |
Analysis of the quality of contacts and vias in multi-metal fabrication processes of semiconductor devices, method and test chip architecture |
摘要 |
A test chip performs measurements to evaluate the performances of interconnects. In particular, the statistical failure distribution, the electromigration and the leakage current are measured. An algorithm detects a via failure at any of the available n metal layers. The test chip includes a ROM memory array. The vias to be measured are formed in the columns of the array. Via or contact failures are detected by forcing a predetermined current through both an array column and a reference column. The failure analysis is obtained by comparing the resulting voltage drops.
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申请公布号 |
US7304485(B2) |
申请公布日期 |
2007.12.04 |
申请号 |
US20040850834 |
申请日期 |
2004.05.21 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
CAPPELLETTI PAOLO;MAURELLI ALFONSO |
分类号 |
G01R31/28;G11C29/02;H01L23/544 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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