| 摘要 |
A memory system using data inversion scheme is provided to reduce power consumption by using an LVCMOS(Low Voltage CMOS) and a POD(Pseudo Open Drain) selectively. A first inversion controller unit(108) generates a first inversion control signal, when an operation frequency of a semiconductor memory device is below a reference frequency. A second inversion controller unit(116) generates a second inversion control signal, when the operation frequency is above the reference frequency. A data inversion/non-inversion unit(124) outputs output data by inverting or non-inverting bits of internal output data received from a memory cell array continuously, in response to the first or the second inversion control signal. A flag output unit(126) outputs a flag signal indicating inversion of the output data, in response to the first or the second inversion control signal. A data output unit(134) drives data input/output pads with an LVCMOS on the ground of the output data outputted from the data inversion/non-inversion part when the operation frequency is below the reference frequency, and drives the data input/output pads with a POD on the ground of the output data outputted from the data inversion/non-inversion part when the operation frequency is above the reference frequency.
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