| 摘要 |
A delay locked loop circuit capable of reducing a bang-bang jitter is provided to reduce the bang-bang jitter in an output clock signal outputted from the delay locked loop circuit, by disabling a phase detector and a variable delay circuit by using detection result of a signal outputted from the phase detector after fine lock. A phase detector(325) outputs a first up signal when the phase of a reference clock signal lags behind the phase of a feedback clock signal, and outputs a first down signal when the phase of the reference clock signal leads the phase of the feedback clock signal. A first detection unit(400) generates a second up signal activated when the number of the first up signals is above 2, and generates a second down signal activated when the number of the first down signal is above 2. A second detection unit(335) detects whether the first up signal and the first down signal are outputted in turn, and generates a detection signal activated when the first up signal outputted in turn is detected. A delay unit(345) delays the feedback clock signal to be synchronized to the reference clock signal, in response to the activated detection signal. A variable delay circuit(310) includes a fine lock part(320) and a coarse lock part(315) synchronizing the reference clock signal and the feedback clock signal by delaying the reference clock signal, in response to a control signal generated on the ground of the activated second up signal or the activated second down signal. |
