| 摘要 |
A PASSIVE COMPONENT INTEGRATED CIRCUIT CHIP (10) FORMED ON AN INSULATIVE SUBSTRATE (12) INCLUDES A FIRST CONDUCTIVE METALLIC LAYER (14) ON A MAJOR SURFACE OF THE SUBSTRATE; A LAYER OF DIELECTRIC MATERIAL (16A, 16B) ON TOP OF THE FIRST CONDUCTIVE METALLIC LAYER (14); A SECOND CONDUCTIVE METALLIC LAYER (18) ON TOP OF THE FORMATION OF DIELECTRIC MATERIAL (16A, 16B); A LAYER OF INSULATIVE MATERIAL (20A, 20B) ON TOP OF THE LAYER OF DIELECTRIC MATERIAL (16A, 16B) AND ON AND AROUND THE SECOND CONDUCTIVE METALLIC LAYER (18), BUT NOT COMPLETELY COVERING THE SECOND CONDUCTIVE METTALLIC LAYER (18); A CONDUCTIVE VIA IN CONTACT WITH A PORTION OF THE SECOND CONDUCTIVE CONDUCTIVE METALLIC LAYER (18) LEFT UNCOVERED BY THE LAYER OF INSULATIVE MATERIAL (20A, 20B); A RESISTENT LAYER (24) ON TOP OF THE LAYER OF INSULATIVE MATERIAL (20, 20B) AND IN CONTACT WITH THE THE CONDUCTIVE VIA (22); A CONDUCTIVE CONTACT (26) IN CONTACT WITH THE RESISTANT LAYER (24); AND A PASSIVATION LAYER (28) ON TOP OF THE RESISTIVE LAYER (24) SO AS TO PROVIDED A SEAL BETWEEN THE RESISTIVE LAYER (24) AND THE CONDUCTIVE CONTACT (26). CONDUCTIVE END TERMINATIONS (30A, 30B) ARE ADVANTAGEOUSLY FORMED ON THE ENDS OF THE SUBSTRATE TO TERMINATE SELECTED CONDUCTIVE CONTACTS AND/OR CONDUCTIVE METALLIC LAYERS.
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