<p>A method and device for power reduction. The device includes a first group (20) of latches located within at least one normal region (40) of an integrated circuit, and second group (30) of latches that are located within at least one retention region (50) of the integrated circuit. The area of the at least one normal region (40) is larger than an area of the at least one retention region (50). The first group (20) of latches is adapted to latch data signals. The second group of latches is adapted to store information representative of the data signals while the first group (20) of latches is deactivated and is further adapted to send to the first group (20) of latches said information when the first group of latches (20) is reactivated.</p>
申请公布号
WO2007135487(A1)
申请公布日期
2007.11.29
申请号
WO2006IB51611
申请日期
2006.05.19
申请人
FREESCALE SEMICONDUCTOR, INC.;PRIEL, MICHAEL;KUZMIN, DAN;ROZEN, ANTON